The present invention relates to a method and/or architecture for memory self time circuits generally and, more particularly, to a method and/or architecture for power supply degradation compensation for memory self time circuits.
Referring to FIG. 1, a block diagram of a memory device 10 having a dual dummy path architecture is shown. The memory device 10 includes a first memory core 12a and a second memory core 12b, each having an array of memory cells for storage and retrieval of data. The array of memory cells is arranged in rows and columns. The rows of memory cells are coupled through wordlines and the columns of memory cells are coupled through bitlines. Each column can have a single bitline (for single-ended memory cells) or a complementary bitline pair (for dual-ended memory cells). The memory device 10 includes a row or wordline decoder 14 (including a plurality of wordline drivers), a control logic circuit 16, and a number of precharge/column multiplexer circuits 20 that decode an address for accessing a particular location of the memory arrays 12a and 12b. Sense amplifiers 22 are enabled to sense the data from the memory cells in the array on the bitlines or bitline pairs. The sense amplifiers 22 present the data to a number of latches 24.
The latching of the data must be delayed for a period of time after an access cycle commences to ensure that the data from the sense amplifiers 22 is valid. Part of the delay is the result of RC delay in the wordlines due to the capacitance of the memory cells that are electrically coupled to the wordlines in each row. Similarly, RC delay is also produced in the columns of the memory cores 12a and 12b due to the capacitance of the memory cells that are electrically coupled to the bitlines in each column. Each access to a particular memory cell includes (i) a delay between the assertion of the wordline corresponding to the memory cell and the activation of the memory cell, and (ii) a delay between the activation of the memory cell and the discharge of the bitline or bitline pair to which it is connected. The data from the sense amplifiers 22 is not valid until after the delays have expired.
Timing control can be implemented to prevent the latching of the data from the sense amplifiers 22 prior to the expiration of an appropriate delay. A worst-case delay can be used to ensure that the data being latched is valid. In addition, the sense amplifiers 22 can consume an appreciable amount of power while activated. The-timing control can be provided to deactivate (shut down) the data sense amplifiers 22 as soon as possible after the data has been latched.
A conventional method for providing the timing control for the data sense amplifiers 22 is the inclusion of self-timing circuitry. The self-timing circuitry can provide a timing control signal that indicates when data from the sense amplifiers 22 of the memory cores 12a and 12b can be latched and when the sense amplifiers 22 can be deactivated. The self-timing circuitry of the memory device 10 includes a dummy bitcell 26a, a dummy bitcell 26b, a dummy sense amplifier 28a, and a dummy sense amplifier 28b. The dummy bitcells 26a and 26b are located in the upper outer corners of the memory cores 12a and 12b, respectively, since a memory cell that is located furthest from a given wordline driver and a given sense amplifier 22 can have the worst-case RC delay. As used herein, the term dummy bitcell refers to a bitcell that is implemented to simulate the operational delays of the other (real) bitcells of the memory device 10. The term dummy sense amplifier refers to a sense amplifier that is implemented in conjunction with a dummy bitcell to simulate the operational delays of the other (real) sense amplifiers 22 of the memory device 10.
The RC delays of the memory cores 12a and 12b are not the only sources of delay in the memory device 10 that can cause failure. Any sources of variation that make the memory self time path delay differ from the actual memory path delay can result in a memory failure. One such source of variation is power supply degradation.
The memory device 10 has a power ring 30 connected to a supply voltage VDD and a power ring 32 connected to a supply ground VSS. The power rings 30 and 32 are positioned around the periphery of the memory 10. The power ring 30 may receive the supply voltage VDD via a number of strap connections 34. The power ring 32 may receive the supply ground VSS via a number of strap connections 36. The supply voltage VDD and the supply ground VSS can be the power supply voltage and ground, respectively, for the memory device 10.
Because of the close proximity of the dummy bitcells 26a and 26b and dummy sense amplifiers 28a and 28b to the power supply rings 30 and 32, the supply voltage VDD and the supply ground VSS presented to the dummy bitcells 26a and 26b and dummy sense amplifiers 28a and 28b are at the most ideal levels. However, the supply voltage VDD and the supply ground VSS presented to the real bitcells and sense amplifiers 22 of the memory device 10 can be degraded (i.e., at less than ideal levels). The degradation of the supply voltage VDD and/or the supply ground VSS can cause the data path (i.e., the real bitcells and/or the real sense amplifiers 22) to have a slower read than the self time path (i.e., the dummy bitcells 26a and 26b and the dummy sense amplifiers 28a and 28b).
A conventional method for memory array self time path delay compensation includes the addition of a delay (e.g., a delay string) to compensate for any variation caused by sources that make the memory self time path delay different than the actual memory path delay. One source of the delay variation is the variation in a supply voltage and/or a supply ground between the elements in the memory self time path (i.e., the dummy bitcells 26a and 26b, the dummy sense amplifiers 28a and 28b, the self time wordline, etc.) and the elements in the memory data path (i.e., bitlines, wordlines, sense amplifiers 22, etc.).
However, the added delay string can have a voltage dependency that does not track the voltage dependency of the memory self time path. In addition, some analog sense amplifiers can have a steep performance rolloff as the power supply voltage VDD drops extremely low. Although the sense amplifiers 22 may still function at extremely low supply voltage VDD, if the delay for activation of the sense amplifier 22 is a strong function of the supply voltage VDD, any variation between the supply voltage VDD to the actual sense amplifiers 22 and the supply voltage to the dummy sense amplifiers 28a and 28b can have a high probability of causing the memory 10 to fail. The steep performance rolloff at low supply voltages exhibited by some analog sense amplifier architectures cannot be adequately compensated for by the addition of a delay string.
It would be desirable to have a method and/or architecture for memory self time circuits that compensates for supply voltage variations and degradation.
The present invention concerns a self-timing memory circuit with supply degradation compensation comprising a first self-timing circuit and a second self-timing circuit. The first self-timing circuit may be configured to generate a first signal that may be minimally affected by power supply degradation and/or variation. The second self-timing circuit may be configured to generate a second signal, where an effect of the power supply degradation and/or variation on the second signal is maximized.
The objects, features and advantages of the present invention include providing a method and/or architecture for power supply degradation compensation for memory self time circuits that may (i) improve the stability of memory self time circuits at low level supply voltages, (ii) compensate for analog sense amplifier rolloff, (iii) ensure that valid data is latched, (iv) ensure that sense amplifiers are not turned off prematurely, and/or (v) compensate for worst case supply voltage and/or ground degradation.